The voltage applied to the conductive polysilicon or "poly" layer gate of field effect transistors (FET's) controls the primary current flow between the spaced apart source and drain semiconductor silicon regions. In PMOS transistor elements P type silicon source and drain regions are formed in an N type silicon substrate or well. In NMOS transistor elements N type source and drain regions are formed in a P well. The source and drain regions are therefore separated by a channel of opposite conductivity semiconductor material. An insulating layer is then formed over the surface. For each MOS transistor element the conductive poly layer gate is formed over the insulating layer, overlies the channel, and overlaps the source and drain regions.
The dimensions of the polysilicon layer gate are important factors in determining the channel resistance between the source and drain regions of an MOS transistor element and therefore the transistor current carrying capacity or drive. The poly layer gate dimension in the source/drain current flow direction is referred to as the gate length formed over a corresponding channel length. For a constant gate width and channel width, the channel resistance is higher and transistor element drive is lower for a longer gate length and longer channel length between the source and drain regions. Conversely the channel resistance is lower and transistor element drive higher for a shorter gate length and shorter channel length between the source and drain regions.
In the fabrication of the MOS IC transistor elements there is considerable process variation in the poly gate length. This dimension of the poly gate is largely determined by exposure and etching steps. There is typically accompanying variation in the exposure step and in the etching rate of the gate forming polysilicon layer. As a result the operating characteristics of the MOS transistor elements may substantially vary across a wafer, from wafer to wafer, from lot to lot, and across a reticle.
Prior art structures devised for monitoring this process variation are known as "Murray Daggers." Polysilicon Murray Daggers are apparently distributed across the wafer for visually indicating the greater or lesser extent of the poly etch. A simple polysilicon Murray Dagger structure 10 is shown in FIG. 1. The poly etching occurs on all sides of the structure and the cumulative etching at a particular location on a wafer is reflected by the number of stepped or graduated coupling widths B,C,D,E . . . entirely etched away on the right of the "dagger" lead structure, or conversely, the number remaining. The prior use of this Murray Dagger structure 10 is limited to use as a monitor only for visual inspection or electrical indication of process variation using the primary lead IA and secondary leads 0B,0C,0D,0E . . . .
The Murray Dagger structure 10 of FIG. 1 may be characterized more generally as being constructed in a configuration with graduated coupling widths B,C,D,E . . . forming a graduated range of respective etchable dimensions arranged in an electrically coupled sequence from a widest coupling width B to a narrowest coupling width E.. which in this case is the coupling width H. A primary lead IA is electrically coupled at one end of the lead structure 10 adjacent to the widest coupling width B. A plurality of secondary leads 0B,0C,0D,0E . . . is distributed along the electrically coupled sequence of graduated coupling widths The graduated coupling widths B,C,D,E . . . of the lead structure 10 electrically couple the secondary leads 0B,0C,0D,0E . . . to the primary lead IA through respective incremental portions of the electrically coupled sequence of graduated coupling widths B,C,D,E . . . . As noted above the prior art use of this structure is limited to visual inspection or electrical indication of IC fabrication process variation in exposure and etching steps according to the electrical continuity detected between the primary lead IA and any remaining secondary leads 0B,0C,0D,0E . . . .
The only U.S. patent reference of interest of which applicant is aware is U.S. Pat. No. 4,583,111 assigned by James M. Early to Fairchild Semiconductor Corporation. Of interest to the examination of this patent application is the circuit configuration in FIG. 9. The ground and power busses are in elongate stepped configurations.
Each bus services multiple logic gates and the width of the step of each step segment of the elongate stepped bus configuration is proportional to the current carried at that location of the bus. The current density in each bus is therefore maintained at a constant level with uniform voltage gradient. The ground and power busses are placed side by side and oppositely oriented in the stepped directions so that the widths are complementary to each other and "nested." The effective constant width of the pair of nested busses is substantially less than two conventional busses.
The elongate stepped configuration bus structures of James Early, however, are not intended for process monitoring or process control. They are not structures for reflecting differential or variable etching. They are constant configuration metal layers intended to maintain constant current density and reduce geometry. They are not intended to be subject to the selective and sometimes uncontrolled process etching of polysilicon for compensation purposes as in the present invention.